? semiconductor components industries, llc, 2015 september, 2015 ? rev. 3 1 publication order number: nb3rl02/d nb3rl02 low phase-noise two-channel clock fanout buffer the nb3rl02 is a low?skew, low jitter 1:2 clock fan?out buffer, ideal for use in portable end?equipment, such as mobile phones. with integrated ldo and output control circuitry. the mclk_in pin has an ac coupling capacitor and will directly accept a square or sine wave clock input, such as a temperature compensated crystal oscillator (tcxo). the minimum acceptable input amplitude of the sine wave is 300 mv peak?to?peak. the two clock outputs are enabled by control inputs clk_req1 and clk_req2. the nb3rl02 has an integrated low?drop?out (ldo) voltage regulator which accepts input voltages from 2.3 v to 5.5 v and outputs 1.8 v at i out = 50 ma. this 1.8 v supply is externally available to provide regulated power to peripheral devices, such as a tcxo. the adaptive clock output buffers offer controlled slew?rate over a wide capacitive loading range which minimizes emi emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. the nb3rl02 is offered in a 0.4 mm pitch wafer?level?chip?scale (wlcs) package and is optimized for very low standby current consumption. features ? low additive noise: ? ?149 dbc/hz at 10 khz offset phase noise ? 0.37 ps (rms) output jitter ? limited output slew rate for emi reduction (1 ns to 5 ns/rise/fall time for 10?50 pf loads) ? regulated 1.8 v output supply available for external clock source, ie. tcx0 ? ultra?small package: ? 8?ball: 0.4 mm pitch wlcs ? esd performance exceeds jesd 22 ? 2000 v human?body model (a1 14?a) ? 200 v machine model (a1 15?a) ? 1000 v charged?device model (jesd22?c101?a level iii) ? these are pb?free devices applications ? cellular phones ? global positioning systems (gps) wlcsp8 case 499bq marking diagrams www. onsemi.com see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information rl = specific device code yy = year ww = work week = pb?free package rlyyww logic diagram
nb3rl02 www. onsemi.com 2 12 c b a d figure 1. pinout (top view) (package ? flip chip) die pads face down on pcb a2 b2 c2 d2 a1 d1 c1 b1 table 1. pin description ball no. name i/o description a1 vbatt i input to internal ldo a2 clk_out1 o clock output 1 b1 vldo o 1.8 v supply for nb3rl02 and external tcxo b2 clk_req1 i clock request from peripheral 1 c1 mclk_in i master clock input c2 clk_req2 i clock request from peripheral 2 d1 gnd ? ground d2 clk_out2 o clock output 2 table 2. function table inputs outputs clk_req1 clk_req2 mclk_in clk_out1 clk_out2 vldo l l x l l 0 v l h clk l clk 1.8 v h l clk clk l 1.8 v h h clk clk clk 1.8 v
nb3rl02 www. onsemi.com 3 table 3. absolute maximum ratings symbol parameter condition min max unit v batt v batt voltage range (note 1) ?0.3 7 v voltage range (note 2) clk_req_1/2, mclk_in ?0.3 v batt + 0.3 v v ldo , clk_out_1/2 (note 1) ?0.3 v batt + 0.3 i ik input clamp current at v batt , clk_req_1/2, and mclk_in v i < 0 ?50 ma i o continuous output current clk_out1/2 20 ma continuous current through gnd, v batt , v l - do continuous current through gnd, v batt , v ldo 50 ma esd rating human?body model 2000 v charged?device model 1000 machine model 200 t j operating virtual junction temperature ?40 150 c t a operating ambient temperature range ?40 85 c t stg storage temperature range ?55 150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. the input negative?voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. all voltage values are with respect to network ground terminal. table 4. recommended operating conditions (note 3) symbol parameter min max unit v batt input voltage v batt 2.3 5.5 v v i input voltage amplitude mclk_in, clk_req1/2 0 1.89 v v o output voltage clk_out1/2 0 1.8 v v ih high?level input voltage clk_req1/2 1.3 1.89 v v il low?level input voltage clk_req1/2 0 0.5 v i oh high?level output current, dc current ?8 ma i ol low?level output current, dc current 8 ma 3. all unused inputs of the device must be held at v cc or gnd to ensure proper device operation.
nb3rl02 www. onsemi.com 4 table 5. electrical characteristics ( t a = ?40 c to +85 c ) symbol parameter test conditions min typ max unit ldo v out ldo output voltage i out = 50 ma 1.71 1.8 1.89 v c ldo external load capacitance 1 10 f i out(sc) short circuit output current r l = 0 100 ma i out(pk) peak output current v batt = 2.3 v, v ldo = v out ? 5% 55 100 ma psr power supply rejection v batt = 2.3v, i out = 2 ma f in = 217 hz and 1 khz 60 db f in = 3.25 mhz 40 t su ldo start?up time v batt = 2.3 v , c ldo = 1 f, clk_req_n to v ldo = 1.71 v 0.2 ms v batt = 5.5 v , c ldo = 10 f, clk_req_n to v ldo = 1.71 v 1 ms power consumption i sb standby current device in standby (all vclk_req_n = 0 v) 0.2 1 a i ccs static current consumption device active but not switching, v clk_reqn = h 0.4 1 ma i ob output buffer average current f in = 26 mhz, c load = 50 pf 4.2 ma c pd output power dissipation capacitance f in = 26 mhz 44 pf mclk_in input i i mclk_in, clk_req_1/2 leakage current v i = v ldo or gnd 1 a c i mclk_in capacitance f in = 26 mhz 3.75 pf r i mclk_in impedance f in = 26 mhz 5 k f in mclk_in frequency range 10 26 52 mhz mclk_in lvcmos source phase noise f in = 26 mhz, tr/tf 1 ns 1 khz offset ?140 dbc/hz 10 khz offset ?149 100 khz offset ?153 1 mhz offset ?151 additive jitter f in = 26 mhz, v pp = 0.8 v, bw = 10 khz ? 5 mhz 0.37 ps (rms) t dl mclk_in to clk_out_n propagation delay 10 ns dc l output duty cycle f in = 26 mhz, dc in = 50% 45 50 55 % note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm.
nb3rl02 www. onsemi.com 5 table 5. electrical characteristics ( t a = ?40 c to +85 c ) symbol unit max typ min test conditions parameter mclk_in sinusoidal source v ma input amplitude 0.3 1.8 v phase noise f in = 26 mhz, v ma = 1.8 v pp 1 khz offset ?138 dbc/hz 10 khz offset ?146 100 khz offset ?151 1 mhz offset ?149 f in = 26 mhz, v ma = 0.8 v pp 1 khz offset ?138 10 khz offset ?146 100 khz offset ?150 1 mhz offset ?148 additive jitter f in = 26 mhz, v ma = 1.8 v pp , bw = 10 khz ? 5 mhz 0.37 ps (rms) t ds mclk_in to clk_out_1/2 propagation delay 12 ns dc output duty cycle f in = 26 mhz, v ma > 1.8 v pp 45 50 55 % clk_out_n outputs t r 20% to 80% rise time c l = 10 pf to 50 pf 1 5 ns t f 20% to 80% fall time c l = 10 pf to 50 pf 1 5 ns t sk channel?to?channel skew c l = 10 pf to 50 pf, (c l1 = c l2 ) ?0.5 0.5 ns v oh high?level output voltage i oh = ?100 a, reference to v ldo ?0.1 v i oh = ?8 ma 1.2 v ol low?level output voltage i ol = 20 a 0.2 v i ol = 8 ma 0.55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm.
nb3rl02 www. onsemi.com 6 application information typical application a typical mobile application for the nb3rl02 is shown in figure 2. an external low noise tcxo clock source is powered by the nb3rl02?s 1.8 v regulated ldo and is buffered to drive a mobile gps receiver and wlan transceiver. each peripheral can independently request an active clock by asserting a clock request line (clk_req1 or clk_req2). figure 2. mobile application when both clock request lines are logic low, the nb3rl02 enters a current-saving shutdown mode. in this mode, the ldo output goes to 0 v and turns off the tcxo. also, the unpowered clk_out1 and clk_out2 outputs are pulled to gnd. when the nb3rl02 receives a high from either peripheral clk_reqn, the 1.8 v ldo output is enabled and will power the tcxo. the output of the tcxo can be a square wave, sine wave, or clipped sine wave and is converted to a buffered square wave. input clock to output square wave generator figure 3 shows the mclk_in input having an internal ac coupling capacitor. this allows either a square or sine wave signal to be directly connected from a tcxo. therefore, an external series capacitor is not required. mclk _in c mclk figure 3. input stage the clock frequency band of the nb3rl02 is 10 mhz to 52 mhz with all performance metrics specified at 26 mhz. typical input sinusoidal signal amplitude is 0.8 v pp for specified performance, but amplitudes as low as 0.3 v pp are acceptable, but with reduced phase noise and jitter performance. clk_out1 and clk_out2 outputs the clk_out1 and clk_out2 outputs drive 1.8 v lvcmos levels with rise/fall times within 1 ns to 5 ns with load capacitors between 10 pf and 50 pf. these relatively slow edge r ates will minimize emi radiation into the system. when not requested, each output is set to low to avoid false clocking of the load device. ldo the integrated low noise 1.8 v ldo provides power internal to the nb3rl02 as well as a power source for an external clock such as a tcx0. the input range of the ldo allows the device to be powered directly from a single cell li battery. the ldo is enabled when either of the clk_reqn signals is high. when disabled, the device turns off the ldo and enters a low power shutdown mode consuming less than 1 a from the battery. the ldo requires an output decoupling capacitor in the range of 1 f to 10 f for compensation and high frequency psr. an input bypass capacitor of 1 f or larger is recommended .
nb3rl02 www. onsemi.com 7 ordering information device temperature range package shipping ? NB3RL02FCT2G ?40 c to 85 c wlcsp8 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb3rl02 www. onsemi.com 8 package dimensions wlcsp8, 1.57x0.77 case 499bq issue a seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 0.77 bsc e b 0.21 0.25 e 0.40 bsc 0.50 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 8x b 12 d c b 0.10 c a1 c 0.13 0.17 1.57 bsc pitch 0.23 8x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.10 c 2x top view side view bottom view note 3 recommended package outline e pitch a 8x a e/2 a3 detail a a2 die coat a2 a3 0.025 bsc 0.30 ref on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nb3rl02/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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